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customer approval sheet company name model a015an05 v0 customer approved title : name : approval for specifications only (spec. ver. ) approval for specifications and es sample (spec. ver. ) approval for specifications and cs sample (spec. ver. ) customer remark : auo pm : p/n : comment : www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m unipac optoelectronics corp. do c . ve rs i o n : 0 . 6 b to ta l p a g e s : 3 1 da t e : 2 0 0 8 . 1 0 . 1 5 model name a015an05 v0 planned lifetime: 2008/01 ~ 2010/12 phase-out control: 2010/06 ~ 2010/12 eol schedule: 2010/12 no t e : t h e c o n t e n t o f t h i s sp e c if ic a t io n i s s u b j e c t t o c h a n g e . ? 2 0 0 7 a u o p t ro n ic s a ll ri g h t s r e se r ve d , product specifications 1.5 color tft-lcd module < > prelim inary specifica tion < > final specification www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 0 / 31 0 record of revision version revise date p a g e content 0 2007/10/30 first draft 5 add vgh vgoff_l and vgoff_h voltage spec 0.1 2007/11/15 23~24 update fig8 and fig9 3 renamed pin29~pin31 cs/sda/scl to csb /sda/scl , an d update note2 4 add pin18~pin20 and pin29~pin31 initial signal stat e and renamed avss to agnd and add remark description. 5 renamed avss to agnd and add power supply to title and update note description. add note2 6 add note1,note2 and current to title. 7 update table back porch and front porch value 13 update dc-dc converter block diagram. 21~23 add register r5 function 24~25 reversion the description of the application c ircuit 0.2 2008/04/24 26~27 update grb pin and vsync sequence 24~25 update fig8 and fig9 0.3 2008/05/08 5 update comdc min and max value 5 update absolute maximum ratings 0.4 2008/05/23 27 update fig vsync grb pin and r2 d3 bit signal add note description 0.5 2008/07/03 5 update avdd and vcom absolute maxi mum ratings value 8 update max dclk frequency value 18 add note for removing protection film before ra t est 0.6 2008/08/05 20 add note for no stress or attachment on the back o f lcd module 0.6a 2008/09/10 21 correct fig 8 cf pixel shift-left for all even row 18 update 7. electrostatic discharge condition 27 update fig8 28 update fig9 0.6b 2008/10/15 31 update led lifetime www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 1 / 31 1 table of contents a. physical specifications ......................... ................................................... ................................................... ......... 2 b. electrical specifications.......................... ................................................... ................................................... ........ 3 c. optical specifications........................... ................................................... ................................................... ........ 16 e. packing form.................................... ................................................... ................................................... ........... 20 f. outline drawing ................................. ................................................... ................................................... ............ 21 g. appendix........................................ ................................................... ................................................... ............... 22 h. suggested application note....................... ................................................... ................................................... . 23 www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 2 / 31 2 a. physical specifications no. item specification remark 1 display resolution (dot) 280 (w) 220 (h) 2 active area (mm) 29.96 (w) 22.66 (h) 3 screen size (inch) 1.48 (diagonal) 4 dot pitch (mm) 0.107 (w) 0.103 (h) 5 color configuration r. g. b. delta 6 overall dimension (mm) 37.06 (w) 34 (h) 3.04 (d) note 1 7 weight (g) 6 typ 8 panel surface treatment hard coating (3h) note 1: refer to fig. 5 www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 3 / 31 3 b. electrical specifications 1. pin assignment (note1) pin no. symbol i/o description remark 1 vcom i common electrode driving signal 2 vgh c positive power for scan driver 3 v1 c power setting capacitor connect pin 4 v2 c power setting capacitor connect pin 5 vgoff_h c negative power supply (high) for g1~g24 0 outputs 6 vgoff_l c negative power supply (low) for g1~g240 outputs 7 v3 c power setting capacitor connect pin 8 v4 c power setting capacitor connect pin 9 avdd1 c frp level supply 10 frp o frame polarity output for panel vcom 11 gnd p ground pin for digital circuits 12 drv o power transistor gate signal for the boost converter 13 led anode p led anode and power supply for charg e pump 14 fb i / p led cathode and main boost regulator fee dback input 15 vcc p power supply for digital circuits 16 agnd p ground pin for analog circuits 17 avdd p power supply for analog circuits 18 hsync i horizontal sync input. negative polarity 19 vsync i vertical sync input. negative polarity 20 dclk i clock signal; latch data onto line latches at the rising edge 21 dd5 i data input: msb 22 dd4 i data input 23 dd3 i data input 24 dd2 i data input 25 dd1 i data input 26 dd0 i data input: lsb 27 v5 c power setting capacitor connect pin note2 28 grb i global reset pin 29 csb i serial communication chip select note3 30 sda i serial communication data input note3 31 scl i serial communication clock input note3 32 vcc p power supply for digital circuits 33 gnd p ground pin for digital circuits i: input; o: output, p: power note 1: for definition of scanning direction, please refer to figure as follows: note 2:the capacitor of v5(pin27) is needed. note 3: please refer to application note for 3-wire serial communication setting. www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 4 / 31 4 2. equivalent circuit of i/o pin no. & pin name schematics 12.drv 14.fb 18.hsync 19.vsync 20.dclk 21.dd5 22.dd4 23.dd3 24.dd2 25.dd1 26.dd0 29.csb 30.sda 31.scl 28.grb www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 5 / 31 5 3. absolute maximum ratings item symbol condition min. max. unit remark vcc gnd=0v -0.5 5 v supply voltage avdd agnd=0v -0.5 5.5 v vgh agnd=gnd=0v 0 16 v vgoff_h agnd=gnd=0v -10 0 v tft-lcd power voltage vgoff_l agnd=gnd=0v -16 0 v input signal voltage cs,sda,scl,vsync, hsync,dclk,d0~d7 agnd=gnd=0v -0.5 5 v vcom ac output voltage frp agnd=gnd=0v 0 8 v vcom ac power voltage vcac agnd=gnd=0v 0 8 v vcom dc output voltage comdc agnd=gnd=0v 0 5 v vcom input voltage vcom agnd=gnd=0v -2.9 5.6 v v1 agnd=gnd=0v 0 16 v v2 agnd=gnd=0v 0 8 v v3 agnd=gnd=0v 0 16 v v4 agnd=gnd=0v -16 0 v storage temperature tstg - -25 80 ambient temperature operating temperature topa - 0 60 ambient temperature www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 6 / 31 6 4. electrical characteristics a. typical operating conditions (gnd = agnd = 0v) item symbol min. typ. max. unit remark v cc 3.0 3.3 3.6 v power supply av dd 3.0 3.3 3.6 v h level v oh vcc-0.4 output signal voltage l level v ol gnd gnd+0.4 h level v ih 0.7v cc - v cc v input signal voltage l level v il gnd - 0.3v cc v h level ioh 10 ua output current l level iol -10 ua analog stand by current ist 200 ua dclk is stopped v cac 4.4 5.6 5.8 v vcom voltage v cdc 0.30 0.45 0.60 v positive power supply vgh 12 13 14 v negative power supply (low) vgoff_l -14 -13 -12 v negative power supply (high) vgoff_h -8.4 -7.4 -6.4 v b. recommended capacitance values of external capacit or the recommended capacitance values of the external capacitor are shown below. these values should be finally determined only after performing sufficient evaluation on the module. pin name operating value of capacitors ( f) withstanding voltage (v) v5 4.7 to 10 6.3(note) vcc 1 to 10 6.3 avdd 1 to 10 6.3 avdd1 1 to 10 10 vgh 1 to 10 16 vgoff_h, vgoff_l 1 to 10 16 v1, v2 1 to 10 16 v3, v4 1 to 10 16 frp 10 16 led_anode 10 16 note1: the capacitors of v5 (27pin) is needed. note2: typical operating capacitors reference sugge sted reference application circuit www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 7 / 31 7 c. current consumption (gnd = agnd = 0v) parameter symbol condition min. typ. max. unit remark i cc v cc = 3.3v - 2 2.5 m a current i dd av dd = 3.3v - 1.5 2.0 m a note1 note2 note1:this power consumption doesnt include led power consumption. note2:test condition: 8colorbar+grayscale pattern , ups051 mode, dclk=5.67mhz, frame rate:60hz. d. led driving conditions parameter symbol min. typ. max. unit remark i led 20 25 25.5 ma note1 led current i led-an ode 22 25 25.5 ma note2 led voltage v l 6.8 7.8 9 v note3 note1: internal led booster circuit. fb=0.6v note2: external led circuit. fb=0.2v note3: v l = led anode (pin 13), led max. voltage: 1pcs/3.6v, led min. voltage: 1pcs/3.0v. @i led =25ma. 5. input timing ac characteristic (vcc=3.3v, avdd=3.3v, agnd=gnd=0v, ta=-25 ~85 ) parameter symbol min. typ. max. unit remark dclk period time t dclk 37 - - ns hsync period time th 60 63.56 67 us vsync setup time tvst 12 - - ns vsync hold time tvhd 12 - - ns hsync setup time thst 12 - - ns hsync hold time thhd 12 - - ns data setup time thst 12 - - ns data hold time thhd 12 - - ns hsync width thsw 1 1 96 t dclk vsync width tvsw 1 t dclk 1 t dclk 6th dclk duty cycle tcwh/tcwl 40 50 60 % www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 8 / 31 8 6. ac timing a. ups051 timing conditions note1: horizontal display position: available display starts from the data of 63 t dclk when back porch value (t hbp ) set 62. note2: ups051 support interlacing input format note3: ups051 support non-interlacing input format. odd field only or even field only parameter symbol min. typ. max. unit. remark dclk frequency 1/t dclk 5.62 5.67 12 mhz period t h 360 t dclk display period t hd 280 t dclk back porch t hbp 61 62 64 t dclk note1 front porch t hfp 19 18 16 t dclk hsync pulse width t hsw 1 25 56 t dclk odd period even t v 256 262.5 264 t h odd display period even t vd 220 t h odd 23 back porch even t vb 23.5 t h odd 13 19.5 21 front porch even t vf 12.5 19 20.5 t h odd vsync pulse width even t vsw 1 t dclk 3 t h 6 t h - www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 9 / 31 9 ups051 input horizontal timing chart ups051 input horizontal data sequence (even) (odd ) www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 10 / 31 10 hsync vsync valid data valid data data 1 field ( odd ) 1 field ( even ) v display v display v blanking v blanking 1 frame t vb t vb t vd t vd t v t v t vsw ups051 input vertical timing chart www.datasheet.co.kr datasheet pdf - http://www..net/
a015an05 product spec version 0.6b page 11 / 31 b. ups052 timing conditions parameter symbol min. typ. max. unit. remark dclk frequency 1/t dclk 23.3 24.54 25.7 mhz period t h 1560 t dclk display period t hdisp 1280 t dclk back porch t hbp 248 249 251 t dclk front porch t hfp 32 31 29 t dclk hsync pulse width t hsw 1 25 56 t dclk note1 odd period even t v 256 262.5 264 t h odd display period even t vdisp 220 t h odd 23 back porch even t vb 23.5 t h note2 odd 13 19.5 21 front porch even t vf 12.5 19 20.5 t h odd vsync pulse width even t vsw 1 t dclk 3 t h 6 t h - note1: horizontal display position: available display starts from the data of 26 6 t dclk when back porch value (t hbp ) set 249. note2: ups052 support interlacing input format note3: ups052 support non-interlacing input format. odd field only or even field only. www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 12 / 31 r0 invalid data invalid data t hbp t hdisp g0 b0 1280 data t hfp t h = t hbp + t hdisp + t hfp hsync dclk t hsw dm r1 g1 b1 dm ups052 input horizontal timing chart www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 13 / 31 ups052 input vertical timing chart hsync vsync valid data valid data data 1 field ( odd ) 1 field ( even ) v display v display v blanking v blanking 1 frame t vb t vb t vd t vd t v t v t vsw www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 14 / 31 7. 3-wire serial communications for 3-wire serial communication timing, it is shown in fig.6. for register setting, please refer to app lication note. 8. dc-dc converter circuit a015an05 contains one high-power step-up dc-dc conver ter, and a backplane drive circuitry for active matrix tft lcds. the output voltage of the main boo st converter can be set from vcc to 13.5v with external resistors. also, there are a precision 0.6 v reference voltage, a fault detection and a logic s hutdown included in a015an05. a .boost converter a015an05 main boost converter uses a boost pwm arch itecture to produce a positive regulated voltage. please refer to fig. 1 for the dc-dc converter block d iagram. drv fb led_anod e agnd agnd agnd agnd fig. 1 dc-dc converter block diagram in the internal architecture of dc-dc converter as sh own in fig. 2, the feedback voltage (vfb) will connect to the tri-angle waveform comparator, and gene rates the output signal (cp0) which determines the duty cycle for (fdc). www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 15 / 31 fig. 2 dc ck block diagram to reduce the noise affect, cp0 will be processed by d e-bounce circuit. state-machine will generate the duty cycle by cp0 signal. to make sure that vfb can r each default vref quickly, so that state-machine is designed as a discrete step by step function, please refer to fig. 3. if cp0 is low, the duty cycle will work from 0% to 75%, and the maximum f that is 75%. fig. 3 pwm control state diagram b. charge pump block diagram the led_anode voltage is used for internal pump c ircuit to generate vgh/vgoff_h/ vgoff_l/vcac for gate and vcom used. fig. 4 charge pump diagram www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 16 / 31 c. optical specifications item symbol condition min. typ. max. unit remark response time rise fall tr tf =0 - - 25 30 50 60 ms ms note 4 contrast ratio cr at optimized viewing angle 60 150 - note 5, 6 viewing angle top bottom left right c r 1 0 10 30 40 40 - - - - - - - - deg. note 7 brightness (25ma) y l =0 130 170 - cd/m 2 note 8 x =0 (0.26) (0.31) (0.36) white chromaticity y =0 (0.28) (0.33) (0.38) n o t e 1 a m b i e n t t e m p e r a t u r e = 2 5 . note 2 measured in the dark room note 3 measured on the center area of panel with a f ield angle of 1 by topcon luminance meter bm-7, after 10 minutes operation. note 4 definition of response time: output signals of photo detector are measured when t he input signals are changed from black to white (falling time) and from white to black (rising time), respectively. response time is defined as the time interval betwe en the 10% and 90% of amplitudes. refer to the figure as follows. note 5 definition of contrast ratio: contrast ratio is calculated with the following form ula. photo detector output when lcd i s at white state photo detector output when lc d is at black state note 6 white vi = v i50 1.5v black vi = v i50 2.0v means that the analog input signal swings in ph ase with com signal. means that the analog input signal swings out of phase with com signal. v i50: the analog input voltage when transmission is 50% 100% transmission is defined as the transmission of lcd panel when all the input terminals of module are electrically opened. s i g n a l ( r e l a t i v e v a l u e ) "black" tr tf "white" "white" 0% 10% 90% 100% contrast ratio (cr) = www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 17 / 31 note 7 definition of viewing angle: refer to the figure as follows. note 8 measured at the center area of the panel when all the input terminals of lcd panel are electrica lly opened. www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 18 / 31 d. reliability test items no. test items conditions remark 1 high temperature storage t a = 8 0 240hrs 2 low temperature storage ta = - 2 5 240hrs 3 high temperature operation t a = 6 0 240hrs 4 low temperature operation t a = 0 240hrs 5 high temperature and high humidity t a = 6 0 . 9 0 % r h 240hrs operation 6 heat shock - 2 5 ~ 8 0 , 5 0 c y c les, 2hrs/cycle non-operation 7 electrostatic discharge air-mode : +/- 8kv contact-mode : +/- 4kv note.2, 3 8 vibration (with carton) random vibration: 0.015g 2 /hz from 5~200hz C 6db/octave from 200~500hz iec 68-34 9 drop (with carton) height: 60cm 1 co rner, 3 edges, 6 surfaces note1 ta: ambient temperature. make sure protection film(s) on top of polarizer or ba ck of lcd module is/are removed before ra test. note2: esd testing flow as the below, note 3. esd testing method. ambient: 24~26 , 56~65%rh instruments:noisekeness-2000, operation system: cx40fl-b and adapter a027dn01 vg test mode: operating mode, test pattern: colorbar+8 gray scale test method: contact discharge: 150pf(330?) 1sec, 5 points, 10 time s/point air discharge: 150pf(330?) 1sec, 5 points, 10 times/p oint test point: lcd power on, functional check electrostatic discharge functional check & judge the results www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 19 / 31 display area bezel auo 1 2 3 4 5 the metal casing is connected to power supply ground (0v) at four corners. all register commands are repeating transfer. www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 20 / 31 e. packing form www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 21 / 31 f. outline drawing note: any stress or attachment on the back of the lcd module is forbidden. . fig. 5 outline dimension of tft-lcd module www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 22 / 31 g. appendix fig. 7 panel color filter alignment fig. 6 3-wire programming function timing www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 23 / 31 h. suggested application note a015an05 is designed with smart integration advance (sia) concept for dsc application. this panel integrated not only source driver & gate driver, bu t also built in power generator and embedded serial communication interface for the function setting. a015an05 is supported by two kinds of input timin g format: ups051 and ups052. customers can use 3-wire serial port for setting register and select d ifferent timing for their own design feature. in this document, we list essential parameters fo r configuration. please follow our recommend settin g to achieve the best performance. in the last page, we provide application circuit to drive a015an05. for a015an05 driving circuit design, you just nee d input one set of power 3.3v, because the charge-p ump circuit inside the driver ic produces vgh & vgl. t he external peripheral is very simple and good for saving bom cost for customers. 1. 3-wire serial communication ac timing parameter symbol min. typ. max. unit serial clock tsck 320 - ns scl pulse duty tscw 40 50 60 % serial data setup time tist 120 - - ns serial data hold time tiht 120 - - ns serial clock high/low tssw 120 - - ns chip select distinguish tcd 1 - - us time that the csb to vsync tcv 1 - - us 2. the configuration of serial data at sda terminal is at below msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 register address data 3. recommend register table for ups051 timing x =>dont care address no. description d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 24 / 31 r0 scan direction 0 0 0 0 0 x x x x x x x x x 0 1 r1 data setting 0 0 1 0 0 x x x x x x x x x 0 0 r2 source ic setting 0 1 0 0 0 x x x x x x x 1 1 0 0 r3 timing select 0 1 1 0 0 x x x x x x x x 0 0 0 r4 vcac level setting 1 0 0 0 0 x x x x x x x x 1 1 0 r5 hblk setting 1 0 1 0 0 x x x x x x x x x 0 0 www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 25 / 31 4. recommend register table for ups052 timing x=>dont care 5. register detail description a. register r0 bit function d0 up/down scan direction: 0 => down to up 1 => up to down d1 left/right scan direction: 0 => left to right 1 =>right to left b. register r1 bit function d0 0 =>when ups051 mode selected 1 =>when ups052 mode selected d1 always fixed at 0 c. register r2 bit function d0 always fixed at 0 d1 always fixed at 0 d2 standby mode setting: 0 => turn off driver & d cdc 1 => normal operating d3 global reset setting: 0 =>driver control register is in reset state, al l setting to default value. 1 =>normal operating; d. register r3 bit function d0 0 => to select ups051 timing 1 => to select ups052 timing d1 always fixed at 0 d2 always fixed at 0 address no. description d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r0 scan direction 0 0 0 0 0 x x x x x x x x x 0 1 r1 data setting 0 0 1 0 0 x x x x x x x x x 0 1 r2 source ic setting 0 1 0 0 0 x x x x x x x 1 1 0 0 r3 timing select 0 1 1 0 0 x x x x x x x x 0 0 1 r4 vcac level setting 1 0 0 0 0 x x x x x x x x 1 1 0 r5 hblk setting 1 0 1 0 0 x x x x x x x x x 0 0 www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 26 / 31 e. register r4 bit function d0 always fixed at 0 d1 always fixed at 1 d2 always fixed at 1 set vcom ac level = 5.6v (amplitude) f. register r5 bit function d1~d0 select the horizontal input delay timing dl1 dl0 no. level 0 0 +0 0 1 -1 1 0 +1 1 1 +2 unit: dclk www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 27 / 31 suggested reference application circuit (1) internal led booster circuit the integrated driver ic provides build-in led boost er controller, dc-dc charge pump, and vcom driver. see fig. 8 for the application circuit. the recomme nded capacitance values of the external capacitor please refer to page 5. the capacitors of 411 will be used shrinkage ic. led , r406 and ic build in on panel cxld120 (led cathode) 3 2 1 q2 5h n01ss extern al-switch 1 i_led_anode i_led fb ic r402 000a smd1206 agn d led_anode c408 1uf vgof f _l avdd c25 10uf r12 10k dd1 avdd1 dd4 c404 1uf vc2 vsy n c drv vgof f _l vc4 vc2 c406 1uf csb dgn d c100 0. 01uf vgof f _h dd2 dd3 33 33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 09 09 08 08 07 07 06 06 05 05 04 04 03 03 02 02 01 01 u 206 con 33 dr v frp vc4 vc1 vcc vcc c402 10uf vc1 c403 1uf q1 fmmt618 scl d100 fs1j3 vgh fb h sy n c vc3 c407 1uf vgof f _h vc3 c405 1uf l100 47uh dclk sw sda dd0 avdd1 grb r401 24 dd5 r100 12k led_anode c300 0.1uf c401 1uf led1 dgn d agn d r405 1k c410 1uf grb vcc vcom vcom open vgof f _l r403 6. 2k avdd r404 20k c409 10uf 1 2 l101 330uh vcc 1 2 3 vr100 100k frp c411 4.7uf vc5 dgnd r406 180 3. 3v vcc 3.3v fig. 8 typical application circuit note: c25 & r12 are new adding external components. c25 => to stable the avdd power r12 => used for discharge avdd power faster q2 to control backlight on/off function external-switch1 h backlight on external-switch1 l backlight off please refer to suggestion power and standby on/off sequence. www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 28 / 31 external led circuit connect to led driv er's fb vcom r506 180 led , r506 and ic build in on panel 3 2 1 q1 5hn01ss external-switch2 c507 1uf vgof f_l i_led_anode i_led fb r502 000a smd1206 ic agnd open vgof f _l avdd r503 6.2k c500 1uf r500 10k avdd dd1 avdd1 dd4 c503 1uf vc2 vsy nc vgof f _l vc4 vc2 c505 1uf csb dgnd dd2 vgof f _h dd3 33 33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 09 09 08 08 07 07 06 06 05 05 04 04 03 03 02 02 01 01 u207 con33 frp vc1 vc4 vcc vcc c501 10uf vc1 c502 1uf scl (led cathode) r504 20k fb vgh hsy nc vc3 c506 1uf vc3 vgof f _h c504 1uf dclk sda grb avdd1 dd0 r501 52 dd5 led_anode frp led1 dgnd c508 10uf agnd r505 1k c509 1uf grb 3.3v vcom d300 udzs 9.1b(9.1v) 1 2 l4 330uh 3.3v dgnd 1 2 3 vr101 100k led_anode vc5 c510 4.7uf fig. 9 external led driver circuit note: q1 to control backlight on/off function external-switch2 h backlight on external-switch2 l backlight off please refer to suggestion power and standby on/off sequence. power supply vcc (typical 3.3v) and avdd (typical 3. 3v) are required to provide driver ic power and generate all necessary voltages for lcd related circ uits. we recommend the external led driver circuit provide a constant 25ma for led backlight unit.we suggest the r501 resister value is greater than 30 ohm to t urn off drv signal.the capacitors of c510 will be u sed shrinkage ic. www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 29 / 31 suggestion power on/off sequence (1) internal led booster circuit (2) external led circuit we recommend power on/off sequence that base on di fferential application circuit to make sure power on/ off function can work successfully in every time power on. note: in standby mode, vsync signal will dont care, but we suggestion vsync is disable. www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 30 / 31 suggestion standby on/off sequence (1) internal led booster circuit note: xx means dont care this signal. (2) external led circuit note: xx means dont care this signal. we recommend standby on/off sequence that base on dif ferential application circuit to make sure function can work successfully. www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this pr per shall not be reproduced, copied, or transformed to any other forms without permission fro m au optronics corp. a015an05 v0 product spec version 0.6b page 31 / 31 i. appendix C led life time data www.datasheet.co.kr datasheet pdf - http://www..net/

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